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Bumping ＆ WLP

Through the Bumping and RDL technology of Wafer Level Packaging, the I/O re-layout and solder / copper pillar bumps on the surface of the wafer are used to realize the bump processing of Flip-Chip

BGA Package

BGA(Ball Grid Array): Interconnection of chip and substrate is realized by using Die bond/Wire bond or advanced normal chip combine with Flip chip named Hybrid BGA technology

QFN/QFP Lead Frame Package

QFN (Quad Flat No-Lead Package) and QFP (Quad Flat Package)： Base on copper Lead Frame QFN and QFP packages with large exposed pads in the center of the package for thermal conduction

Flip-Chip

FCCSP/FCBGA (Flip-chip CSP/BGA): Advanced high-precision Flip chip level packages with Cu pillar or Solder bump by flipping the chip over and attaching it to the substrate

SiP（System in Package）

SiP(System in Package): From the traditional Single chip with passive components, developing to Multi chip multifunctional chip with passive components, including normal chip (Die bond/Wire bond) and Flip chip hybrid packaging technology